The present trend in semiconductor technology is toward very large scale integration of devices with high speed and low power dissipation. To achieve this, it is essential that the devices be made as small as possible by making the vertical junction structure shallower and reducing horizontal geometry. Precise shallow junction profiles can be achieved with ion implantation of dopant species and their subsequent annealing with a thermal cycle. Device horizontal geometry depends to a large extent on the lithographic tools available. U.S. Pat. No. 3,929,528 to Davidson et al. discloses a conventional non-self-aligned process which uses various selective etching and deposition techniques to define device regions. Davidson et al. is directed to the use of a P+ etch stop layer for providing sufficiently planar surface for further processing. Davidson et al. indicate, however, that a P+ etch stop layer will result in undesirable effects due to out diffusion during annealing and seek to solve this problem by completely removing the layer by polishing or etching prior to the anneal.
Within a given lithographic straint, the use of a self-aligned process can greatly improve device performance. The use of a self-aligned polysilicon base is a powerful technique in that it allows self registration of the emitter implant to the polysilicon base contact and allows the base contact to be moved from the device base area onto the polysilicon thus reducing the device base area. Examples of prior art patents describing the conventional self-aligned extrinsic base regions for forming high performance bipolar transistors are: U.S. Pat. Nos. 4,381,953; 4,338,662; 4,641,416; and 4,703,554.
A further trend in semiconductor technology is the use of low temperature epitaxy (LTE), typically performed in an ultra high vacuum chemical vapor deposition (UHV/CVD) process. The use of LTE is very advantageous in that it permits the deposition of epitaxial layers at low temperatures which allows shallow base profiles to be maintained and permits the deposition of compound semiconductor layers such as SiGe that are impossible with ion implantation.
Several different types of self-aligned base processes have been developed. One type is the single polysilicon process in which the extrinsic base is formed of polysilicon and the emitter is implanted. A second is the double polysilicon layer process in which both the extrinsic base and the emitter are formed from polysilicon. Both processes have their advantages and disadvantages and the selection of the process will depend on subsequent end-use of the transistor being formed.
In the fabrication of bipolar transistors, it would be advantageous to use the LTE process in fabricating a double polysilicon self-aligned device. However, attempts to use LTE in double polysilicon technology have resulted in problems because the deposition is not selective, making it difficult to fabricate self-aligned devices. In the formation of an epitaxial base bipolar transistor, if the LTE base layer deposition takes place after the formation of the extrinsic base stack, several approaches have been investigated including the base after sidewall approach and the high pressure oxidation (HIPOX) removal method. However, these methods are not suitable for the new trend towards forming heterojunction bipolar transistors, such as SiGe base transistors, because the success of these two methods depends strongly on specific diffusion and oxidation steps. The deposition of the LTE base layer before the extrinsic base stack was heretofore impossible because of its lack of an intrinsic base etch stop when patterning the polysilicon stack. Thus, there is a need for a method for forming an LTE base transistor using the double polysilicon self-aligned process technology with a minimum of changes that is suitable for both homojunction and heterojunction base transistors.